This invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device for use as a NOR-type mask ROM (Read Only Memory).
Recently, use has been made of a NOR-type mask ROM as a large-capacity semiconductor memory device. The NOR-type mask ROM comprises a plurality of MOS transistors. Each of the MOS transistors has a gate connected to each of word lines arranged in parallel to one another, and a source and a drain formed by N.sup.+ diffusion layers intersecting with the word lines. The MOS transistors are arranged in columns and rows to form an array which will be referred to as a memory cell array. Likewise, the MOS transistors may be referred to as memory cell transistors or simply as memory cells.
Specifically, a conventional semiconductor memory device of the type described comprises, a plurality of primary digit lines and a plurality of subsidiary digit lines, as will later be described in detail. Each of the subsidiary digit lines is formed by an N.sup.+ diffusion layer. Each of the primary digit lines is arranged between each odd-numbered subsidiary digit line and each even-numbered subsidiary digit line next thereto. Between every two adjacent ones of the subsidiary digit lines, a plurality of memory cells comprising MOS transistors are connected with each subsidiary digit line used as a source or a drain. Thus, the memory cells are arranged in columns and rows to form a memory cell array. A gate of each memory cell is connected to each of word lines arranged in parallel to one another. A plurality of block selection MOS transistors are connected to one ends of the odd-numbered subsidiary digit lines at one side of the memory cells, respectively. Each pair of two adjacent ones of the block selection MOS transistors are also connected to each odd-numbered primary digit line interposed therebetween. Gates of the block selection MOS transistors are alternately connected to one and the other of two block selection lines. In each of the block selection MOS transistors, a current path at a channel portion is taken in a direction intersecting with each of the subsidiary digit lines. Likewise, a plurality of block selection MOS transistors are connected to one ends of the even-numbered subsidiary digit lines at one side of the memory cells, respectively. Each pair of two adjacent ones of the block selection MOS transistors are also connected to each even-numbered primary digit line interposed therebetween. Gates of the block selection MOS transistors are alternately connected to one and the other of the above-mentioned two block selection lines. Similarly, in each of the block selection MOS transistors, a current path at a channel portion is taken in a direction intersecting with each of the subsidiary digit lines.
In the above-mentioned circuit structure of the conventional semiconductor memory device, however, each block selection MOS transistor is connected in series to the memory cells. This means that the discharge current for reading information greatly depends on the driving current of the block selection MOS transistor. Accordingly, in order to achieve a high-speed reading operation, it is required to increase the width of the block selection line which defines an area of a part where the channel width of each bank selection MOS transistor is determined. As a result, a chip size is inevitably increased.
In view of the above-mentioned disadvantage in the conventional semiconductor memory device, an improved semiconductor memory device is proposed in Japanese Unexamined Patent Publication No. 104406/1994. As will later be described in detail, the semiconductor memory device disclosed in the above-referenced publication tries to widen the channel width of the block selection MOS transistor without changing the chip area.
In the meanwhile, a recent trend in the mask ROM is to increase an operation speed and, on the other hand, to reduce a supply voltage without decreasing an operation speed currently achieved. In accordance with such trend, the block selection MOS transistor must have a greater current drivability. In addition, in order to meet the use of so-called multilevel cells in which a plurality of threshold values are set in each memory cell transistor, it is required to perform a reading operation from a memory cell transistor having a high threshold value. Also in view of this requirement, the block selection MOS transistor must have a greater current drivability.
In the semiconductor memory device described in the above-referenced publication, the channel width of the block selection MOS transistor can be increased twice at maximum as compared with the conventional semiconductor memory device described earlier in this specification. In order to further increase the current drivability, the width of the block selection line must be widened. This results in an increase of the chip size. In addition, since an increased area of the N.sup.+ diffusion layer is connected to the primary digit line through a contact portion, the capacity applied to the primary digit line is increased. This makes it difficult to achieve a high-speed reading operation.